# to use this example type # regmaker.pl -p projectname -v example.v -vh example.vh -m example.m -w example.html -c example.h example.txt GLOBAL NOPIPE 1 BASEADDR 28000000 SECTION SPI ADDR 100 NAME SPI_CONTROL REGDES spcr RESET 0x10 BIT 7 RW SPIE Serial Peripheral Interrupt Enable When the Serial Peripheral Interrupt Enable is set ('1') and the Serial Peripheral Interrupt Flag in the status register is set, the host is interrupted. Setting this bit while the SPIF flag is set generates an interrupt. '0' = SPI interrupts disabled '1' = SPI interrupts enabled BIT 6 RW SPE Serial Peripheral Enable When the Serial Peripheral Enable bit is set ('1'), the core is enabled. When it is cleared ('0'), the core is disabled. The core only transfers data when the core is enabled. '0' = SPI core disabled '1' = SPI core enabled BIT 5 RW DWOM Port D Wired-OR Mode BIT 4 RO MSTR Master Mode Select When the Master Mode Select bit is set ('1'), the core is a master device. When it is cleared ('0'), it is a slave device. Currently only master mode is supported. This bit is set, and can not be cleared. '0' = Slave mode '1' = Master mode This bit is unused in this design BIT 3 RW CPOL Clock Polarity The Clock Polarity bit, together with the Clock Phase bit, determines the transfer mode. Refer to the SPI Transfers section for more information BIT 2 RW CPHA Clock Phase The Clock Phase bit, together with the Clock Polarity bit, determines the transfer mode. Refer to the SPI Transfers section for more information. BIT 1:0 RW SPR SPI Clock Rate Select These bits select the SPI clock [sck_o] rate. Refer to the ESPR bits in the Extension Register for more information. ADDR 104 NAME SPI_STATUS REGDES spsr BIT 7 RW SPIF Serial Peripheral Interrupt Flag The Serial Peripheral Interrupt Flag is set upon completion of a transfer block. If SPIF is asserted ('1') and SPIE is set, an interrupt is generated. To clear the interrupt write the status register with the SPIF bit set ('1'). BIT 6 RW WCOL Write Collision The Write Collision flag is set when the Serial Peripheral Data register is written to, while the Write FIFO is full. To clear the Write Collision flag write the status register with the WCOL bit set ('1'). BIT 3 RO WFFULL Write FIFO Full The Write FIFO Full bit shows the status of the write FIFO. BIT 2 RO WFEMPTY Write FIFO Empty The Write FIFO empty bit shows the status of the write FIFO. BIT 1 RO RFFULL Read FIFO Full The Read FIFO Full bit shows the status of the read FIFO. BIT 0 RO RFEMPTY Read FIFO Empty The Read FIFO empty bit shows the status of the read FIFO. SECTION GPIO ADDR 200 NAME GPIO_RESET_ON_LO RWTYPE WO REGDES To assert the reset signal to gpio_signal[n], set gpioResetOn[n] to '1'. Bits written with '0' will have no effect on the IO signals. For IOs configured as inputs, reset will hold the sampled input values at '0'. For output IOs, the signals will be driven with '0'. This register is write-only, so reading it will return zero. BIT 15:0 Assert Reset ADDR 204 NAME GPIO_RESET_ON_HI RWTYPE WO BIT 15:0 Assert Reset ADDR 210 NAME GPIO_SIG_DIR_LO RWTYPE RW REGDES Selects the input or output mode of the GPIO signals. To configure gpio_signal[n] to be an output, set gpioSigDir[n] to '1'. For input configuration, write the bit with '0'. Reading this register returns the current configuration of the IO signals. BIT 15:0 Signal Direction (1=output) SECTION I2C_MASTER ADDR 300 RESET 0xFFFF NAME I2C_CLOCK_PRESCALE_LO REGDES i2c0p BIT 7:0 This register is used to prescale the SCL clock line. Prescale is a 16-it value, and this register is used to access the lower byte. Due to the structure of the I2C interface, the core uses a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change the value of the prescale register only when the 'EN' bit is cleared. Example: proc_clock = 32MHz, desired I2C speed = 100KHz prescale = ((32*1000)/(5*100)) -1 = 63 = 0x3F ADDR 304 NAME I2C_CLOCK_PRESCALE_HI REGDES i2c0p BIT 7:0 This register is used to prescale the SCL clock line. Prescale is a 16-it value, and this register is used to access the upper byte. See I2C_CLOCK_PRESCALE_LO for more details. ADDR 308 NAME I2C_CONTROL REGDES i2c0c BIT 7 RW EN, I2C core enable bit. When set to '1', the core is enabled. When set to '0', the core is disabled. The core responds to new commands only when the 'EN' bit is set. Pending commands are finished. Clear the 'EN' bit only when no transfer is in progress, i.e. after a STOP command, or when the command register has the STO bit set. When halted during a transfer, the core can hang the I2C bus. BIT 6 RW IEN, I2C core interrupt enable bit. When set to '1', interrupt is enabled. When set to '0', interrupt is disabled. BIT 5:0 RO RESERVED SECTION DDR ADDR 400 NAME DDR_MEMC_STATUS RWTYPE RO REGDES Memory Controller Status Register BIT 31:13 Read undefined. BIT 12 memory_banks1 - This returns part of the definition of the number of banks that the controller supports on each chip. BIT 11:10 exclusive_monitors - Returns the number of exclusive access monitor resources implemented in the memory controller: 2'b00 = 0 monitors 2'b01 = 1 monitor 2'b10 = 2 monitors 2'b11 = 4 monitors. BIT 9 memory_banks0 - This returns part of the definition of the number of banks that the controller supports on each chip. BIT 8:7 memory_chips - Returns the number of different chip selects that the memory controller supports: 2'b00 = 1 chip 2'b01 = 2 chips 2'b10 = 3 chip 2'b11 = 4 chips BIT 6:4 memory_type - Returns the SDRAM that the memory controller supports: 3'b000 = SDR SDRAM 3'b001 = DDR SDRAM 3'b011 = Mobile DDR SDRAM 3'b000 = SDR SDRAM 3'b001 = DDR SDRAM 3'b011 = Mobile DDR SDRAM 3'b010 = eDRAM 3'b1xx = Reserved. If Mobile DDR SDRAM or SDR SDRAM or an eDRAM is supported, the cas_half_cycle bit at address offset 0x14 is ignored. BIT 3:2 memory_width - Returns the width of the external memory: 2'b00 = 16-bit 2'b01 = 32-bit 2'b10 = 64-bit 2'b11 = Reserved. BIT 1:0 memc_status - Returns the state of the memory controller: 2'b00 = Config 2'b01 = Ready 2'b10 = Paused 2'b11 = Low_power.