www.kwcpa.com/tools
This page contains a number of tools I have written which are useful for ASIC design. They are written in perl, or ANSI C, and all have the GNU GPL license. I hope you find them as useful as I do. All I ask is that you drop me a note if you find them helpful. Thanks! /jeff
Note: My logs indicate that there are dozens of downloads every month, yet very few people drop me a note. If you like my tools, or even if you don't, please drop me a note and let me know what you're using and what you'd like to see changed. Also, let me know if you wanted to be notified when updates are posted.
General Tools Verilog Tools Backend Tools
General Tools:
PROCWAIT.PL is a perl script used for flexible job control. It can be used to start jobs based on the start or completion of another job, or on the creation of a semiphore file. It is used to allow jobs to trigger one-another, either on the same machine or across machines. [last update 2/19/04]
READER.C was written to allow easy viewing of very large files. It can be used to read files too big to load into an editor, or to view big files over a slow (i.e., dialup) connection. The program reads in a large file very quickly and provides one- or two- character commands that allow you to move through it, and search it. It can be optimized to search through certain user-specified strings (like "Error") quickly. It can also write portions of the file to another file. [last update 3/9/04]
CAD_EVAL.PL uses the information in cadence.log license files to provide a usage report. The report consists of two parts. The first part is a listing, by input file, of the amount of time N licenses were in use for all N between 1 and the maximum number of licenses used. The second part is a combined histogram that shows peak number of licenses used for each week. [last update 6/24/04]
Verilog Tools:
BEGEND.C parses a verilog file for begin/end and case/endcase statements, and produces a report that shows the level of nesting for each type of nesting at every line. This is useful for debugging nesting errors. [last update 2/5/03]
DCBUILD.PL is a Perl script which uses multiple calls of dc_shell to create a bottom-up build script, and a complete report of your module hierarchy. [last update 6/19/03]
IFDEF.C parses verilog or C files for various forms of ifdef's. Under user control some of these ifdefs can be executed and the results written to a file. This allows you to see what your file would look like if certain (or all) ifdefs are executed. The list of ifdefs to be executed can be collected from the source file, from a user-generated file, or from a simulator opts file. IFDEF.C also finds ifdef/endif nesting errors. [last update 11/19/08]
MERGECOV.C merges line coverage results generated by Cadence's NC Verilog NC-COV coverage tool (nccov). Instead of a binary database, it uses report files as source. This allows the merging of slightly dissimilar designs, and other flexibilities not afforded by the Cadence tool. It also allows you to determine the incremental coverage provided by each individual test. [last update 2/23/04]
MODSPLIT.PL splits verilog source files which contain multiple modules into multiple files, one module per file. A common header can be added, and the tool is smart about handling code between modules. An older version, written in C, but with some extra features is available here. [last update 3/30/09]
REGMAKER.PL (formerly regparse.pl) generates register descriptions in different formats from a common textual input. Outputs include HTML, Verilog, C headers, and Matlab headers. Registers can be de-populated, and logical register size does not have to match Physical register size. Regmaker is rich with options for customizing the different views, and the C and Matlab code is customizable. [last update 3/29/09]
Backend Tools:
GETPATHS.PL This perl script can quickly read a Primetime or Magma timing report and generate sorted lists of all the paths (startpoint, endpoint, slack). [last update 4/21/04]
MAGMA_GEN_ECO.PL This perl script can generate the .TCL for a variety of Magma ECOs. Using a command language it can perform buffer insertion, buffer removal, cell replacement, and metal fixes. It can also generate hold fixes (delay buffer insertion) directly from a PrimeTime report. [last update 7/7/07 - Many cool improvements!]
PTCMP.C compares the output from two Primetime runs. It reads in the path, group, type, and, slack of each entry in the first report, and tries to find a corresponding path, group, and type in the second report. When it does, it compares the slack, and only reports differences that exceed a user-defined limit. I have found this useful near the end of a design when very small changes are being made to the layout, but the timing has to be totally re-blessed. [last update 3/9/04]
TRACE_SCAN_CHAIN.PL will take a flat (typically post-route) netlist, and a signal name at the end of a scan chain, and will trace out the entire scan chain. The output is a report listing the makeup of the scan chain, with clock domain crossings highlighted. It is optimized for Artisan libraries, but all library specifics are abstracted into lists at the top of the script which can be customized by the user. Note: This script has been tested with Magma 4.0 netlists. [last update 6/4/04]
A great site for other ASIC tools can be found at http://www.veripool.com.
PROCWAIT.PL is a perl script used for flexible job control. It can be used to start jobs based on the start or completion of another job, or on the creation of a semiphore file. It is used to allow jobs to trigger one-another, either on the same machine or across machines. [last update 2/19/04]
READER.C was written to allow easy viewing of very large files. It can be used to read files too big to load into an editor, or to view big files over a slow (i.e., dialup) connection. The program reads in a large file very quickly and provides one- or two- character commands that allow you to move through it, and search it. It can be optimized to search through certain user-specified strings (like "Error") quickly. It can also write portions of the file to another file. [last update 3/9/04]
CAD_EVAL.PL uses the information in cadence.log license files to provide a usage report. The report consists of two parts. The first part is a listing, by input file, of the amount of time N licenses were in use for all N between 1 and the maximum number of licenses used. The second part is a combined histogram that shows peak number of licenses used for each week. [last update 6/24/04]
Verilog Tools:
BEGEND.C parses a verilog file for begin/end and case/endcase statements, and produces a report that shows the level of nesting for each type of nesting at every line. This is useful for debugging nesting errors. [last update 2/5/03]
DCBUILD.PL is a Perl script which uses multiple calls of dc_shell to create a bottom-up build script, and a complete report of your module hierarchy. [last update 6/19/03]
IFDEF.C parses verilog or C files for various forms of ifdef's. Under user control some of these ifdefs can be executed and the results written to a file. This allows you to see what your file would look like if certain (or all) ifdefs are executed. The list of ifdefs to be executed can be collected from the source file, from a user-generated file, or from a simulator opts file. IFDEF.C also finds ifdef/endif nesting errors. [last update 11/19/08]
MERGECOV.C merges line coverage results generated by Cadence's NC Verilog NC-COV coverage tool (nccov). Instead of a binary database, it uses report files as source. This allows the merging of slightly dissimilar designs, and other flexibilities not afforded by the Cadence tool. It also allows you to determine the incremental coverage provided by each individual test. [last update 2/23/04]
MODSPLIT.PL splits verilog source files which contain multiple modules into multiple files, one module per file. A common header can be added, and the tool is smart about handling code between modules. An older version, written in C, but with some extra features is available here. [last update 3/30/09]
REGMAKER.PL (formerly regparse.pl) generates register descriptions in different formats from a common textual input. Outputs include HTML, Verilog, C headers, and Matlab headers. Registers can be de-populated, and logical register size does not have to match Physical register size. Regmaker is rich with options for customizing the different views, and the C and Matlab code is customizable. [last update 3/29/09]
Backend Tools:
GETPATHS.PL This perl script can quickly read a Primetime or Magma timing report and generate sorted lists of all the paths (startpoint, endpoint, slack). [last update 4/21/04]
MAGMA_GEN_ECO.PL This perl script can generate the .TCL for a variety of Magma ECOs. Using a command language it can perform buffer insertion, buffer removal, cell replacement, and metal fixes. It can also generate hold fixes (delay buffer insertion) directly from a PrimeTime report. [last update 7/7/07 - Many cool improvements!]
PTCMP.C compares the output from two Primetime runs. It reads in the path, group, type, and, slack of each entry in the first report, and tries to find a corresponding path, group, and type in the second report. When it does, it compares the slack, and only reports differences that exceed a user-defined limit. I have found this useful near the end of a design when very small changes are being made to the layout, but the timing has to be totally re-blessed. [last update 3/9/04]
TRACE_SCAN_CHAIN.PL will take a flat (typically post-route) netlist, and a signal name at the end of a scan chain, and will trace out the entire scan chain. The output is a report listing the makeup of the scan chain, with clock domain crossings highlighted. It is optimized for Artisan libraries, but all library specifics are abstracted into lists at the top of the script which can be customized by the user. Note: This script has been tested with Magma 4.0 netlists. [last update 6/4/04]
A great site for other ASIC tools can be found at http://www.veripool.com.